© 2012 Lattice Semiconductor Corp. Avalon® -MM Interface Signals 6. 3 CSMA/CD LAN Model As noted earlier, the XGMII interface consists of 4 lanes of 8 bits. What i want to do is i want to feed the PCS with xgmii_tx signals, connect the txn/txp to rxn/rxp respectively and monitor the xgmii_rx signals whether they are the same as xgmii_tx. 5Gb/s 8B/10B encoded - 3. 802. PCS) IP GT IP Serial. We are using the 10G/25G Ethernet Subsystem for 10G with PCS only. Prodigy 120 points. The 5GBASE-R PCS provides all services required by the XGMII including Encoding (decoding) of XGMII data octets to (from) 64B/66B blocks for communication with the underlying PMA. Status Signals. 5MHz or 64-bit data path at 156. 介质. > > 1. Figure 54–1 shows the relationship of the 10GBASE-BX1 PMD sublayers and MDI to the ISO/IECThe specification requires each of the four XAUI lanes to transfer 8-bit data and 1-bit wide control code at both the positive and negative edge (DDR) of the 156. 3, Clause 47. Download Core Submit Issue. 15The 100G Ethernet Verification IP is compliant with IEEE 802. Simulation and verification. 2 and XAUI. The RGMII interface has been designed in accordance with the standards and specifications agreed in theThe present clauses in 802. The TLK2206 supports both 4/5-bit RTBI as well as 8/10-bit parallel interface using DDR clocking. Connection to the SerDes is through a configu-rable 16-, 20-, 32-, 40-, or 64-bit interface. The system data width, that is, the width of the interface to the user logic, is c onfigured as 64 bits. Additionally, for applications requiring 20 Gbps throughput, Intel FPGA's XAUI PHY solution can support DXAUI (4 x 6. 1 Online Version Send Feedback UG-20071 ID: 683876 Version: 2021. The IP core is compatible with the RGMII specification v2. Section Content. XGMII, as defi ned in IEEE Std 802. XGMII Signals 6. This is not related to the API info. SD 4. , the received data. 1G/10GbE Control and Status Interfaces 5. Interface Signals 7. 3. XAUI Align Character Skew Support of 30 Bit Times at Chip Pins; MDIO: IEEE 802. 3ba standard. The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802. USGMII supports eight 10M/100M/1G network ports over 10Gbps SERDES between MAC and PHY. 3u）。介质独立的意思是指，MAC与PHY之间的通信不受具体传输介质（双绞线或光纤等）的影响，任何MAC和PHY都可以通过MII接口互连。 MAC与PHY之间的MII连接可以是可插拔的连…Interface Avalon-ST XGMII/ GMII/MII 10M/100M/ LL 10GbE MAC PHY Serial Interface Note: Intel FPGAs implement and support the LL 10GbE Media Access Control (MAC) and Multi-Rate Ethernet PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T (1G/2. 5GPII Word For off chip stuff, these days nobody uses XGMII, it's either XAUI (4x3. I see three alternatives that would allow us to go forward to > TF ballot. XGMII Interface 10G 32-bit MODE(MAC+ $;, /LWH :UDSSHU SERDES DATA MUX. 1. 3125 Gbps/32-bit = 322. Calibration 8. Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included. Session. I see three alternatives that would allow us to go forward to > TF ballot. PG251 October 4, 2017 Product Specification Introduction The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with a mechanism to carry a single port of 10M, 100M, 1G, 2. Section Content Features Release Information LL. 5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Updated for Intel ® Quartus Prime Design Suite: 19. 10GBASE-KR is an Ethernet defined interface intended to enable 10. Of course I do it all FS, Unit test, Integration testing, and customer testing. 2019年2月12日 閲覧。 ^ “Serial-GMII Specification” (2005年4月27日). This is the ACPI _DSD Implementation Guide. By grouping them in a QSGMII, only one SERDES interface is needed to be used, so only 1 Tx and 1 Rx (2 in total) differential lines are routed. • No internal interface is super-rated, • XGMII rate is preserved (312. 3u）。. The IP provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10. 4. This block contains the signals TXD (64. The XGMII design is now provided with the 10-Gig MAC Core in CORE Generator. 4 SGMII interfaces mean 4 Tx and 4 Rx (8 in total) differential lines between the MAC and the PHY. 5G/5G/10G Multi-rate PHY. 3-2012 clause 45;Support to extend the IEEE 802. The Client-side interface is a 64-bit AXI-S and comes with a 64-bit XGMII interfaces on the PHY side. 5 volts per EIA/JESD8-6 and select from the options > within that specification. The XgmiiSink receives XGMII traffic, including monitoring internal interfaces. 3125 Gbps serial single channel PHY over a backplane. The purpose is to utilize one QuadSGMII serdes to connect multiple SGMII chips, not a single. XGMII Mapping to Standard SDR XGMII Data. XAUI. > 3. 1. The MII is standardized by IEEE 802. I'm currently reading the IEEE XGMII specification (IEEE Std 802. Avalon® Memory-Mapped Interface Signals 6. Transceiver Status and Reconfiguration Signals 6. With experience of SSTL, I believe we can define the HSTL interface in more reasonable time frame. Features. Want to thank TFD for its existence? Tell a friend about us, add a link to this page, or visit the webmaster's page for free fun content. (MAC), PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T PHY standard devices. After the 10 Gbps data is extracted from the four lanes, it must be formatted in a XGMII interface. The code-group synchronization is achieved upon th e reception of four /K28. It's an attempt to realize the Open RAN concept. VIP Options. 3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface XGMII. XFP光模块标准定义于2002年左右，其内部的收和发方向都带有CDR电路。. to the PCS synchronization specification. Reference HSTL at 1. 19. The 10 Gigabit Ethernet PCS/PMA (10GBASE-R) is a no charge Xilinx LogiCORE which provides a XGMII interface to a 10 Gigabit Ethernet MAC and implements a 10. 1. The 10GBASE-X PCS provides all services required by the XGMII and in support of the 10GBASE-X PMA, including: Definitely not XGMII (32-bit DDR, was never really seen off-chip) or XAUI (4 lanes of 3. 0. The SERDES circuitry is configured to support source synchronous and asynchronous serial data communication for the SGMII interface at 1. XAUI uses four full-duplex serial links operating at 3. This is a 64-bit bus that runs at 156 MHz for 10 Gbps or up to 187. Introduction. Intel PRO/1000 GT PCI network interface controller. 3 is used as the interface between an Ethernet physical layer device and a media access controller. 3125 Gbps serial line rate with 64B/66B encoding 10GBASE-KR and 1000BASE-KX is the electrical backplane physical layer implementation for the 10 Gigabit and 1 Gigabit Ethernet link defined in clause 72 and clause 70. : info: Info Object: REQUIRED. Avalon® -MM Interface Signals 6. supports bi-directional data flow and can be deployed multiple ways: • Interface Conversion: Connect data steams between flight units using XAUI and test systems using 10GigE. We are using the 10G/25G Ethernet Subsystem for 10G with PCS only. Where possible the PIPE specification references the PCI Express base specification specification rather than repeating its content. 1 of the IEEE P802. 3 protocol and MAC specification to an operating speedof 10 Gb/s. authors of this specification disclaim all liability, including liability for infringement of proprietary rights, relating to implementation of information in this. 2. Figure 2-3: Ethernet 1/10G Dynamically Switching 32-bit PCS/PMA IP Block Diagram. This module converts XGMII interface of XGMAC core to high speed serial interface needed by physical interface. 17. Design Example MAC Variant PHY Development Kit 10GBase-R Ethernet 10G Native PHY Intel Arria 10 GX Transceiver SI. Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). The IP core is compatible with the RGMII specification v2. Interface Signals 7. Labels: Labels: Network Management; usxgmii. (See IEEE Std 802. The data are multiplexing to 4 lanes in the physical layer. In case of conflicts, the PCI-Express Base Specification shall supersede the PIPE spec. Both jobs do a lot of work, and have to know a lot. 25MHz PCS layer XGMII interface implemented as 64-bit (single data rate) SDR interface at 156. 3 layer diagram 100Mb/s and above RS. 10 gigabit media-independent interface (XGMII) is a standard defined in IEEE 802. 3) enabled Pattern Gen code for continues sending of packet . If you set the value of the Ethernet PCS interface parameter in the CPRI parameter editor to GMII, your IP core includes this interface. Unlike previous Ethernet. N GMII Electrical Specification Page 8 IEEE P802. IP is needed to interface the Transceiver with the XGMII compliant MAC. RGMII to GMII converter provides the interface between a standard gigabit media independent interface (GMII) to RGMII conversion. com Features See Reference Design Manual • 10 Gbps Ethernet • 10G PHY interface: 64-bit XGMII interface at 156. Release Information 2. XAUI addresses several physical limitations of the XGMII. SerDes TX RX MII Serial Figure 5–1. This is the SDS (Start of Data Stream). 8V devices whose MDC/MDIO ports can withstand this without blowing a hole in the oxide. 1 2 Document Number: DSP0222 3 Date: 2009-07-21 4 Version: 1. PHY /Link interface specification , . 5M transfers/s) • PHY line rate is preserved (10. (See IEEE Std 802. Since we have the datasheet, we can confirm some of the specifications of RK3588, and get additional details: CPU – 4x Cortex-A76 @ up to 2. • Detailed specifications including submodules, verification plan, and release history Related products: • A-XGFIF - Configurable FIFO module • M-XGXS - XGMII to XAUI. The 10GBASE-X PCS provides services to the XGMII in a manner analogous to how the 1000BASE-X PCS provides services to the 1000 Mb/s GMII. Xilinx also has 40G/50G Ethernet Subsystem IP core. The generic nature of this interface facilitates mapping the CoaXPress signaling into the. These documents describe the technical characteristics of the antenna panels on the GPS Block IIR and Block IIR-M satellites. "JUST" <smile>. XGMII Transmission 4. (MAC) with a XGMII (10 Gigabit Media Independent Interface) for incorporation in a customer’s ASIC design. 125Gbps 10GBASE-R Clause 49 (IEEE 64B/66B PCS only) o No IEEE. The 10 Gigabit Media Independent Interface (XGMII) is an interface standard that uses 72 data pins for both RX and TX. The Serial Gigabit Media Independent Interface ( SGMII) is a sequel of MII, a standard interface used to connect an Ethernet MAC-block to a PHY. 3 の第 49 項で定義されている BASE-R PCS/PHY (Physical Coding Sublayer/Physical Layer) を採用し、10M、100M、1G、2. Host Interface Speed Data width # Pins Clock Frequency Transmission Specification QSGMII 4x ≤1. 3-2008 specification. Behavior of the MAC TX in custom preamble mode: Interface Signals 7. 3. // Documentation Portal . This function MAY throw to revert and reject the /// transfer. You may refer to the applicable IEEE802. The 10 Gigabit Media Independent Interface (XGMII) is an interface standard that uses 72 data pins for both RX and TX. There needs to be some way to allow alternate voltages for this interface and still be standards compliant. Check MAC PHY XGMII interface signals, no data sent out from MAC. 7. However, if the XGMII is not implemented, a conforming implementation must behave functionally as though the RS and XGMII were present. USXGMII Subsystem. specification for internal use only. 2. AUTOSAR Interface. 4 Standard, 2. At the Tampa meeting I intend to propose that we just adopt the logic family that the XGMII uses (we might have to put a note in about termination schemes as the MDIO is multi-drop). 3az standard for Energy Efficient Ethernet. 7. Resources Developer Site; Xilinx Wiki; Xilinx Github1 2 Document Number: DSP0222 3 Date: 2009-07-21 4 Version: 1. LightRequest. The most popular variant, 1000BASE-T, is defined by the IEEE 802. Avalon® Memory-Mapped Interface Signals 6. More specifically, physical (PHY) layer 227 provides electrical and physical specifications, including details like pin layouts and signal voltages, for interactions between network device 110 and physical channel 120. 5GPII Implementation as shown does not require much incremental logic Does not preclude implementations that directly map XGMII into PCS Diagram above for IEEE functional specification purposes only 1000BASE-X PHY 2. > > 1. Introduction. The PHY IP core can be used with either Intel® FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156. 10G/25G Ethernet (PCS only) RX_MII alignment. Return to the SSTL specifications of Draft 1. The 10G USXGMII Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel® FPGA IP core operating at 10M, 100M, 1G, 2. . 12. In the FPGA world where the MAC and PHY are implemented in the same chip technically this interface layer is not required, as the MAC and. Includes MAC modules for gigabit and 10G, a 10G PCS/PMA PHY module, and a 10G combination. Return of other than the magic value. 8. 2. 25 Mbps. This solution is designed to the IEEE 802. 5 Gb/s and 5 Gb/s as well as 10 Gb/s. Comcores Ethernet MAC is silicon-proven and designed for easy integration into ASICs and FPGAs. 4 11/18 Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100Support to extend the IEEE 802. The inclusion of a XGMII means that several alternative PHY interfaces are readily supported, including XSBI (10 Gigabit Sixteen Bit Interface) and XAUI. XLGMII is for 40G Interface. This PHY IP core is made available as part of the transceiver functionality of the Intel® FPGAs. The XgmiiSource and XgmiiSink classes can be used to drive, receive, and monitor XGMII traffic. PMA. 1. Avant-E; CertusPro-NX; Certus-NXXGMII Update Page 4 of 12 hmf 11-July-2000 IEEE 802. Code replication/removal of lower rates. In the 10G Ethernet segment, the Universal Serial 10G Media Independent Interface (USXGMII) IP core from Microchip enables building 10GBASE-R solutions on PolarFire. 6. See moreThe XGMII interface, specified by IEEE 802. This specification is targeted towards the requirements of embedded systems. 1. XAUI and XGMII Layers Section Content Transceiver Datapath in a XAUI Configuration XAUI Supported Features Transceiver Clocking and Channel Placement. • The TX state machines needs a check to prevent this from happening. Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). Hello everyone, I am searching for a chip that connects to QuadSGMII on one side and multiple SGMII on the other. We just have to enable FLOW CONTROL on our MAC side. 2023年11月1日 閲覧。 ^ IEEE 802. 4. relevant amba specification accompanying this licence. RGMII uses four-bit wide transmit and receive datapaths, each with its own source synchronous clock. 3125 Gbit/s) • Data throughput is reduced: • inter-frame gaps are increased through extended operation of MPCP, which accounts for FEC parity insertion • Extra IDLEs are deleted in PCS and used to insert FEC partiyText: PHY devices via 10-Gbps media independent interface (XGMII) or 10-Gbps attachment unit interface (XAUI) Management data input/output. AUTOSAR Introduction - Part 2 21-Jul-2021. X20473-0306. Actually - I should amend this answer - XGMII isn't the correct protocol, I think I'm thinking of 10GBASE-R. This version supports HL7 V 2. 6. 1. Network. However, the Altera implementation uses a wider bus interface in connecting a. 0. Transceiver Status and Transceiver Clock Status Signals 6. 1. 3125 Gbps serial line rate with 64B/66B encoding. QuadSGMII to SGMII splitter. 1 R2. 1. The IEEE 802. USGMII Specification. It can be replaced by a resistor-capacitor combination, both of package size 0603. 1. XGMII Encapsulation. Media-Independent Interface（MII、媒体独立インタフェース）は、イーサネットにおいて、MAC (データリンク層デバイス)とPHY (物理層デバイス)とを接続するためのインタフェース。本稿では以下の拡張版を含めて記述する。The XGMII interface defines the 32-bit data and 4-bit wide control character clocked between the MAC/RS and the PCS at both the positive and negative edge (double data rate – DDR) of the 156. Reduced Gigabit Media Independent Interface (RGMII) (Reduced GMII) is the most common interface as it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection speeds at the PHY layer. XGMII Signals 6. Once you see an SDS, it means that the exchange of ordered sets has finished. The 10GBASE-X PCS provides services to the XGMII in a manner analogous to how the 1000BASE-X PCS provides services to the 1000 Mb/s GMII. As a result the above text only applies to XGMII 10 Gb/s operation and IEEE 802. The RGMII interface can be either a MAC interface or a media interface. Reference HSTL at 1. OpenCores 10GE MAC Core Specification 1/19/2013 RX Enqueue Engine In the RX Enqueue Engine, the RC layer monitors the XGMII interface for fault conditions and pass the status to the Fault State-Machine. With a mixture of 100Mbps and 1GbE nodes, system designers prefer to develop common, reusable platforms that support both types of nodes. interface is the XGMII that is defined in Clause 46. XLGMII is for 40G Interface. This specification defines USGMII. 3125 Gbps serial single channel PHY providing a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification. Transceiver Reconfiguration 8. (2) The XGMII extender sublayer (XGXS) extends the distance of XGMII when used with XUAI and provides the data conversion between XGMII and XAUI. According to IEEE802. Please refer to PG210. Operating Speed and Status Signals XAUI is standardized instantiation of XGMII Extender (Clause 47) In practical implementations physical interface between MAC and PHY XSBI is an optional physical instantiation of PMA service interface for 10GBASE-R and 10GBASE-W (Clause 51) 16-bit bidirectional interface with source synchronous clock The XGMII interface, specified by IEEE 802. Loading Application. Thanks, I have this problem too. Table 1. Therefore, it is necessary to complete the conversion of GMII to XGMII interface in firmware. In other words, you can say that interfaces can have abstract methods and variables. Supports 10-Gigabit Fibre Channel (10. With experience of SSTL, I believe we can define the HSTL interface in more reasonable time frame. Optional Management Data Interface (MDIO) interface to manage PCS/PMA registers according to specification IEEE 802. Low Latency Ethernet 10G MAC 8. Notably, MII 370 is an interface capable of providing two-way communication between MAC device 350 and PHY device 360. 125 Gbps) or XFI (1x10. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Uses 7 series, Virtex 6, Virtex 5, Virtex 4, and Spartan 6 transceivers running 4 lanes at 3. It's exactly the same as the interface to a 10GBASE-R optical module. 18-199x Revision 2. -Avalon ST TX and RX input/output signals to Avalon ST TX/RX 64 bit adapter. Once you see an SDS, it means that the exchange of ordered sets has finished. XGMII Signals 6. It came into use in 1999, and has replaced Fast. On the opposite side a pair of XGMII interfaces are used to transfer frames between the nfmac10g and the PCS/PMA (or XAUI) core. 1. 3, Clause 47. Received Ethernet bytes are available on the 64-bit XGMII interface (RX_MII_D/C). The specifications and information herein are subject to change without notice. Implements DTE XGXS, PHY XGXS, and 10GBASE-X PCS in a single single encrypted HDL. Open RAN is a generic term that refers to open RAN architectures including open interfaces, virtualization, and use of AI. 1. Unidirectional. 5 V MDIO I/O) RGMII. GMII TBI verification IP is developed by experts in Ethernet, who have. 3. The objectives of the five workstreams are the following: M-HPM (Host Processor Modules) Workstream which involves three specifications: M-FLW (FulL Width HPM) Specify the requirements of a Full Width Host Processor Module (HPM). MII Interface Signals 5. - Wishbone Interface for control. 3-2008 specification. It would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. PHY. Capacities & Specifications. XAUI is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between. UK Tax Strategy. Standardized. 25GMII is similiar to XGMII. Uses two transceivers at 6. USGMII provides flexibility to add new features while maintaining backward compatibility. XFI and SFI electrical specifications respectively apply to XFP and SFP+ system front port optical modules. XAUI v12. PHY Registers. 1 XGMII Interface The XGMII interface connects the Reconciliation Sublayer (RS) with the IP and allows transferring information to/from as defined in Clause 46. Several Physical Coding Sublayers known as 10GBASE-X, 10GBASE-R, and10GBASE-W are specified, as well as significant additional supporting material for a 10 GigabitMedia Independent Interface (XGMII), a 10 Gigabit Attachment. Several Physical Coding Sublayers known as 10GBASE-X, 10GBASE-R, and10GBASE-W are specified, as well as significant additional supporting material for a 10 GigabitMedia Independent Interface (XGMII), a 10 Gigabit Attachment. 3ae-2002). > 3. 6. As far as I understand, of those 72 pins, only 64 are actually data, the remai. 1 Overview This clause defines the logical and electrical characteristics for the Reconciliation Sublayer (RS) and 10Gigabit Media Independent Interface (XGMII) between Ethernet media access controllers and various PHYs. 8V devices whose MDC/MDIO ports can withstand this without blowing a hole in the oxide. 3 Plenary, HSSG meeting, Atlanta, GA 11 10G Service interfaces XGMII is standardized instantiation of PCS interface (Clause 46) XAUI is standardized instantiation of XGMII Extender (Clause 47) In practical implementations physical interface between MAC and PHY XSBI is an optional physical instantiation of PMA service interface10-Gbps Ethernet MAC MegaCore Function user guide ›. Loading Application. 4. 14. Received Ethernet bytes are available on the 64-bit XGMII interface (RX_MII_D/C). com URL: Features. 1G/10GbE PHY Register Definitions 5. This SGMII solution meets the SGMII specification and saves cost and power in systems that have low to high port-count Gigabit Ethernet per device. It differs from GMII by its low-power and low pin count serial interface (commonly referred to as a SerDes ). Resetting Transceiver Channels 5. Reduced Gigabit Media Independent Interface (RGMII) (Reduced GMII) is the most common interface as it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection speeds at the PHY layer. 5G/5G/10Gb Ethernet) PHY. Is there a reference design for for SGMII to GMII core at 2. It is used to achieve abstraction and multiple inheritances in Java using Interface. I would like to get some clarification for the " Universal SXGMII Interface for a Single MultiGigabit Copper Network Port" specification. Networking. Leverages DDR I/O primitives for the optional XGMII interface. 2. 3125Gbps transmission across lossy backplanes. 1. Status Signals. The Reduced Gigabit Media Independent Interface (RGMII) module provides an RGMII interface to an existing Ethernet MAC design with a GMII or TBI interface, for example the Gigabit Ethernet MAC (GEM) available from Cadence Design Foundry. Headlight. The host application requests this xml file from the device and creates a register tree. Two XAUI linkIt would > be a shame for TF ballot to be delayed because of the absence of XGMII > electricals. This is most critical for high density switches and PHY. The XgmiiSource and XgmiiSink classes can be used to drive, receive, and monitor XGMII traffic. These characters are clocked between the MAC/RS and the PCS at both the positive and negative edge (double datarate – DDR) of the 156. Specifications; Documentation; Overview. Instead, they support a 64-bit data and 8-bit control single data rate (SDR) interface between the MAC/RS and the PCS. All transmit data and control. 5 volts per EIA/JESD8-6 and select from the options > within that specification. 2 External interface requirements. The XAUI core is an extension of the XGMII interface and as such there is no data-stripping happening within the core. IEEE Std 802. 3 Clause 46 ratified specification enabling a variety of PHY and MAC chips from different vendors to talk the exact same protocol. 5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP core implements USXGMII PCS based on Cisco specification. 3 is used as the interface between an Ethernet physical layer device and a media access controller. 125Gbps for the XAUI interface. Reconfiguration Signals 6. The satellite manufacturer, Lockheed Martin, compiled the information based on its design specifications and ground test measurements of the antenna panels. Register Access Definition 8. . The XGMII Controller interface block interfaces with the Data rate adaptation block.